1. Field of the Invention
This invention relates to the field of switching voltage regulators, and particularly to multiple-phase DC—DC converters.
2. Description of the Related Art
Advanced microprocessors typically require power supplies that provide a low voltage (e.g., <2 volts) at high current. The trend is for these supply voltages to continue to fall, while the current demand increases.
The load a high speed processor presents to a power supply can go from low to high or vice versa in a very short time, particularly when running demanding software programs. One way in which high currents are provided is with a multiple-phase switching regulator, in which the components of a number (N) of single-phase regulators are repeated to produce N output currents, which are summed together to provide the total output current. The phases are operated in parallel, and are synchronously switched so as to reduce the overall input and output ripple, as well as deliver large output currents.
Ideally, the power supply for a high speed processor will be highly efficient, as well as quickly responsive to changes in load. For a multiple-phase switching regulator to have high efficiency, low ripple currents and low switching frequencies are desired to keep switching losses low. But a regulator having low switching frequencies and ripple currents typically requires the use of large output inductors, and tends to respond slowly to load changes. Transient response is improved with the use of a higher output filter capacitance, but this adds cost and requires space.
Alternatively, a designer can achieve high efficiency using small inductors with a high switching frequency. This allows the converter to respond quickly with a minimal amount of output filter capacitance. However, to deliver high currents, expensive high switching speed components must be used to keep efficiency high, or more phases must be used to lower the current per phase and improve the power losses—again adding cost.
One problem associated with the responsiveness of a switching converter to changes in load is illustrated in FIGS. 1a-1c. A basic DC—DC converter having N phases is shown in FIG. 1a. Each phase includes a pair of switching transistors (MP1a/MP1b, . . . , MPna/MPnb) which are alternately operated to conduct current to and from an output inductor (L1, . . . , Ln) to produce respective phase currents (Ip1, . . . , Ipn). The individual currents are summed together to produce an overall output current Iout, which is filtered with a filter capacitance Cf to provide a regulated output voltage Vout and drive a load 10. A controller 12 provides respective control signals (PWM1, . . . , PWMn) to operate the switching transistors.
The operation of the converter in FIG. 1a under steady-state conditions is shown in FIG. 1b. The phases are enabled in sequence, with each phase enabled once in a period T. The duration of each phase's on-time is given by DT, where D is the duty cycle. When ND<1, the voltages (Vp1, . . . , Vpn) at the junctions of the switching transistor pairs are as shown in FIG. 1b. These voltages result in the phase currents (Ip1, . . . , Ipn) shown. Summing the phase currents together results in output current Iout, which has a ripple current Ir, and produces an output voltage Vout having a ripple voltage Vr. When so arranged, the normal output current ripple slew rate (i.e., slope) when a phase is switched on (i.e., current conducted from VCC to the phase's output inductor), Son, is given by:Son=(1−ND) (VCC/L) amps/second,where VCC is the converter's input voltage. The normal output current ripple slew rate when all phases are switched off (i.e., current conducted from all output inductors to ground), Soff, is given by:Soff=(−ND) (VCC/L) amps/second.
The operation of the converter for a change in output load is shown in FIG. 1c. When the demand for load current (Iload) increases, the duty cycles of one or more phases are increased to provide more DC output current. This can result in more than one phase being on at a time, such that, when the load current increases sharply, the “turn-on” output current slew rate Snt is greater than Son and is given by:
Snt=(M−ND) (VCC/L) amps/second, where M is the number of phases turned on by the change in the output load. This is seen on the plot of Iout, which reflects the transition from Son to Snt as Iout increases (M=2 for the example shown). Also shown on the Iout plot is ripple current Ir, which varies with the difference between Iout and Iload.
However, the “turn-off” output current slew rate, applicable when there is a sharp decrease in load current, is limited to Soff. This results in a large error between Iout and Iload, with the error reduced at the Soff-limited rate. As such, the converter responds faster to a load change increase (load step) than it does to a load change decrease (load release): Vout exhibits a small undershoot 16 during a load step, but a large overshoot 18 of long duration during a load release.
This large overshoot is not acceptable for most designs. By increasing the output filter capacitance Cf, this overshoot can be removed but requires additional cost for the design. This increase in capacitance, however, is not required for the converter's response to a load step.